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o Channel mapping in ROI    registers

o Channel mapping in Trigger    Input Enable tiles registers

Register Names: ACD Channels in GEM

Channel mapping in ROI registers

Table 5: ROI register names and mappings. "Register Name'' give the name of the register the LATC_XML. Each 32-bit register breaks into 2 x 16 bit halves. Each 16 bits is read as a mask. If a bit is set then that ACD channel is in the associated ROI.
Register Name 16 MSB 16 LSB Register Name 16 MSB 16 LSB
r_000_001 000 001 r_002_003 002 003
r_004_010 004 005 r_011_012 011 012
r_013_014 013 014 r_020_021 020 021
r_022_023 022 023 r_024_030 024 030
r_031_032 031 032 r_033_034 033 034
r_040_041 040 041 r_042_043 042 043
r_044 044 NA2 r_100 NA3 100
r_101_102 101 102 r_103_104 103 104
r_110_111 110 111 r_112_113 112 113
r_114_120 114 120 r_121_122 121 122
r_123_124 123 124 r_130 130 NA4
r_200 NA5 200 r_201_202 201 202
r_203_204 203 204 r_210_211 210 211
r_212_213 212 213 r_214_220 214 220
r_221_222 221 222 r_223_224 223 224
r_230 230 NA6 r_300 NA7 300
r_301_302 301 302 r_303_304 303 304
r_310_311 310 311 r_312_313 312 313
r_314_320 314 320 r_321_322 321 322
r_323_324 323 324 r_330 330 NA8
r_400 NA9 400 r_401_402 401 402
r_403_404 403 404 r_110_111 410 411
r_412_413 412 113 r_414_420 414 420
r_121_122 421 422 r_423_424 423 124
r_430 430 NA0 r_500 NA1 500
r_501_502 501 502 r_503_600 503 600
r_601_602 601 602 r_603 603 NA10

Channel mapping in Trigger Input Enable tiles registers

Table 6: Trigger enable tile register names. Each register mask 9 channels. Since each physical channel has 2 PMT this masking requires 18 bits. Bits 0-8 mask the A side PMT, Bits 9-17 mask the B side PMT.
Register Name LSB Channels MSB
tiles_000_013 000 001 002 003 004 010 011 012 013
tiles_014_032 014 020 021 022 023 024 030 031 032
tiles_033_NA3 033 034 040 041 042 043 044 NA2 NA3
tiles_100_113 100 101 102 103 104 110 111 112 113
tiles_114_NA5 114 120 121 122 123 124 130 NA4 NA5
tiles_200_213 200 201 202 203 204 210 211 212 213
tiles_214_NA7 214 220 221 222 223 224 230 NA6 NA7
tiles_300_313 300 301 302 303 304 310 311 312 313
tiles_314_NA9 314 320 321 322 323 324 330 NA8 NA9
tiles_400_413 400 401 402 403 404 410 411 412 413
tiles_414_NA1 414 420 421 422 423 424 430 NA0 NA1
tiles_500_NA10 400 401 402 403 500 501 502 503 NA10

 

Owned by: Eric Charles  
Last updated by: Chuck Patterson 01/22/2008