On This Page

o TRG: Trigger Configuration
o GNL: General LAT-wide    Settings
o ACD: Anti-Coincidence    Detector Settings
o CAL: Calorimeter Settings
o TKR: Tracker Settings

LPA Precincts

This section lists details for each of the LATC precincts, including:
  • Field mapping (if applicable).
  • Configuration methods available.
  • Ancillary files used.
  • Input constants required.

Notes:

  • Group is the hardware component on which the register is located.
  • Instances is the number of specific instances of that register, broken down by the hardware hierarchy.
  • Multiplicity means the number of associated registers with similar names and functionality on each hardware instance.
  • Subsections are the number of independent data on the register.
  • If "Type" is "int'', the register should just be read as a number.
  • If "type'' is 'fields'', the register should be broken into component fields.
  • If "type'' is "mask'', the register is a bit mask where each bit enables or disables a channel or group of channels.

TRG: Trigger Configuration

The trigger configuration is split into two precincts: TRG_GEM, which covers everything except the Region of Interest definitions for the ACD tiles and TRG_ROI, which covers only the Region of Interest definitions.

TRG_GEM: GEM configuration

The TRG_GEM precinct controls almost all the aspect of the Trigger configuration. This includes enabling the various inputs to the trigger, specifying which conditions are allowed to cause a trigger, how those conditions map into the trigger accept messages (TAM) that are sent back to the readout electronics, and the details of the periodic trigger. It is almost certain that the TRG_GEM precinct will have the largest number of different configurations for any precinct.

  • Registers:
    Group Register Name Instances Multiplicity Subsections Type Width (bits)
    GEM conditions 1 32 8 int 32
    GEM configuration 1 1 1 fields 1
    GEM engine 1 16 1 fields 32
    GEM periodic_rate 1 1 1 fields 32
    GEM periodic_mode 1 1 1 fields 2
    GEM periodic_limit 1 1 1 int 32
    GEM window_open_mask 1 1 1 fields 8
    GEM window_width 1 1 1 int 5
    GEM towers 1 4 4 mask 12
    GEM tiles 1 24 2 mask 18
    GEM acd_cno 1 1 1 mask 12
    GEM tower_busy 1 1 1 mask 16
    GEM external 1 1 1 mask 1

    The conditions and engine registers are by far the most complex of GEM registers to configure; they are described in detail below. Also, the mapping of bits to channels in the tiles and towers registers are fairly complicated. Both of these have specialized input XML syntax described below.

    For the other GEM registers that can be split into fields, the breakout of the fields is:

    Field Mask Comments
    configuration
    use_acd_as_trigger 0x00000001 Bit set allows ACD self triggering
    periodic_rate
    prescale 0x00ffffff  
    use_1_pps 0x80000000 Bit set means use 1-pps as counter. Otherwise use 20 MHz.
    periodic_mode
    free_run 0x01  
    window_open_mask
    roi 0x01  
    tkr 0x02  
    calle 0x04  
    calhe 0x08  
    cno 0x10  
    periodic 0x20  
    solicited 0x40  
    external 0x80  

    On the other hand the acd_cno, tower_busy and external registers are just straight bit-masks with LSB corresponding to channel 0.

  • Methods: BCAST
  • Ancillary files: None
  • Constants: None
  • Conditions register rules:
    Since the GEM conditions words has 8 bits, it takes 256 possible values. The conditions registers map each of those 256 values to one of the trigger engines defined by the engine registers. Each of the conditions register breaks into eight 4 bit sections which specify the engine used for that set of conditions. The conditions registers take names from conditions_00_07 to conditions_F8_FF which specify the range of 8 conditions word values mapped in that register. Since many of the GEM conditions are ``un-physical'', rather than specify all 256 values, we specify a set of rules used to create the conditions mapping.

    Each rule for mapping the conditions register is defined in a <rule> XML node under the <GEM_conditions> register node. To define a rule for a mapping the conditions register, at least two things must be specified, the rule number and the engine number the rule maps to. These are given as attributes to the <rule> node called ``number'' and ``engine''. Beyond that, the status of each of the GEM conditions bits may be constrained by assigning ``1'' (must be true), ``0'' (must be false) or ``x'' (don't care) to the attribute corresponding to that bit. The attribute names are: ``roi'', ``tkr'', ``clo'', ``chi'', ``cno'', ``per'', ``sol'', ``ext''.

    An example of rule definitions is:

    •     <GEM_conditions>
      <rule number='0' engine='0' ext='1' sol='x' per='x'
          cno='x' chi='x' clo='x' tkr='x' roi='x'/>
      <rule number='1' engine='1' ext='0' sol='x' per='x'
           cno='x' chi='x' clo='x' tkr='0' roi='1'/>
    <GEM_conditions>

It would map any external triggers to engine 0 regardless of the other bits (128 values would be mapped) and any events with the ``roi'' condition set but not the ``tkr'' into engine 1, regardless of the other values (a further 32 values would be mapped). The mapping algorithm assigns a GEM conditions word value to the first rule that matches. Also, any unclaimed values of the GEM conditions word will be mapped to the next available engine number (engine 2 in the case of the example above).

  • Engine registers:
    The 16 engine nodes are named engine_0 to engine_f and can be defined in <engine> nodes under the <GEM_engine> XML register node. This is done by specifying the engine number and the values for the various register fields.
      <GEM_engine>
        <engine number='0' calstrobe='0' fourrange='0' inhibit='0'
               marker='0' prescale='0' tack='1' zerosuppress='1'/>
        <engine number='1' calstrobe='0' fourrange='0' inhibit='0'
               marker='0' prescale='0' tack='1' zerosuppress='1'/>
      </GEM_engine>

The breakout for the fields in the engine registers is:

Field Mask Comments
prescale 0x000000ff Prescale counter. Accept event when counter reaches 0
inhibit 0x00008000 Bit set means trigger inhibited.
calstrobe 0x00010000 Bit set means issue charge injection strobe.
tack 0x00080000  
four_range 0x00100000 Bit set mean read out all four ranges in CAL
zero_suppress 0x00200000 Bit set means apply zero suppression
marker 0x01c00000 Marker value (0-8) is written to event
destination 0x1e000000  
  • GEM Trigger Input Enable <tower> registers:
    The GEM Trigger Input Enable (TIE) section has four registers to mask the tower triggers. These registers are named <tower_0_3>, <tower_4_7>, <tower_8_b> and <tower_c_f>. Each register has 12 bits which mask the ``tkr'', ``clo'' and ``chi'' lines from each of 4 towers. Since this mapping is somewhat complicated we choose to specify the mask by trigger type. 
    <GEM_towers>
        <tkr_tower_mask>0xffff</tkr_tower_mask>
         <clo_tower_mask>0xffff</clo_tower_mask>
         <chi_tower_mask>0xffff</chi_tower_mask>
       </GEM_towers>
  • GEM Trigger Input Enable <tiles> registers:
    The GEM Trigger Input Enable (TIE) section has 24 registers to mask the ACD inputs. These names and mappings of these registers are listed in appendix B.2. Rather than do anything complicated we specify if the tiles should be masked on not, and which channels should be reversed. 
    <GEM_tiles>
        <enableAll>True</enableAll>
        <exceptTileList>000</exceptTileList>
    </GEM_tiles>

TRG_ROI Veto Region Of Interest configuration

The TRG_ROI precinct sets the ROI mapping in the GEM. In normal operation the ROI mapping details which tiles are associated with with tracker towers. In special acd_as_trigger mode the ROI mapping details the set of tile-tile coincidences with will trigger the LAT. In either case, the TRG_ROI precinct maps the intent from a list of acd channel names to the a set 54 32-bit registers which are interpreted as bit-masks.

  • Registers:
    Group Register Name Instances Multiplicity Subsections Type Width (bits)
    GEM r 1 54 2 mask 32
  • Methods: BCAST
  • Ancillary files: None
  • Constants: None
 

GNL: General LAT-wide settings

The are a few registers in the AEM and TEMs which we can use to do very high level masking and timing control of the LAT. Rather than grouping these registers with the sub-system registers we have chosen to pull them into their own precincts.

GNL_Mode: LAT-wide channel masking

This precinct handles masking off data at the electronics module level.

  • Registers:
    Group Register Name Instances Multiplicity Subsections Type Width (bits)
    AEM aem_configuration 1 1 1 mask 12
    TEM data_masks 16 1 1 mask 16
    TIC tkr_out_mask 16 1 1 mask 16
    TIC tkr_layer_enable 16 2 1 mask 18
    TIC cal_in_mask 16 1 1 mask 16

    The two tkr_layer_enable masks are called "tkr_layer_enable_0'' and "tkr_layer_enable_1'' and specify the tracker layer enables for layers 0-8 and 9-17 respectively.
  • Methods: BCAST
  • Ancillary files: None
  • Constants: None

GNL_Timing: LAT-wide timing settings

This precinct handles timing at the electronics module level. Each electronics modules has a global delay in how it handles the trigger message that can be tuned so the entire LAT is synchronized.

  • Registers:
    Group Register Name Instances Multiplicity Subsections Type Width (bits)
    AEM trgseq 1 1 1 fields 32
    TEM cal_trgseq 16 1 1 fields 32
    TEM tkr_trgseq 16 1 1 fields 16
  • Methods: BCAST
  • Ancillary files: None
  • Constants: None
 

ACD: Anti-Coincidence Detector settings

We have split the ACD configuration into six precincts. The first two handle setting the mode (ACD_Mode) and timing (ACD_Timing) for the ACD and will be done with broadcast settings. The other four precincts (ACD_Bias, ACD_Pha, ACD_Veto, ACD_Hld) handle various settings and thresholds which require input calibrations and will vary on a channel-by-channel basis.

ACD_Mode: ACD channel masking and mode configuration

The ACD_Mode precinct controls masking various aspect of the ACD functionality and configuring the ACD Front-end electronics.

  • Registers:
    Group Register Name Instances Multiplicity Subsections Type Width (bits)
    ARC veto_en 12 2 1 mask 18
    ARC pha_en 12 2 1 mask 18
    ARC max_pha 12 1 1 int 5
    AFE config_reg 12 x 18 1 1 fields 8
    AFE tci_dac 12 x 18 1 1 int 6

    Since ARC registers are 16 bits wide, the veto_en and pha_en registers are both split into two parts, _0 (first 16 bits) and _1 (last two bits). For the sake of specifing LATC intent in the vote file they are treated as a single register.

    The breakout for the fields in the config_reg register is:

    Field Mask Comments
    TCI 0x0002 Bit set enables charge injection
    manual_gain_range 0x0004 Bit set means manual selection of readout range
    high_gain_range 0x0008 Bit set means readout in high range
    veto_discriminator 0x0010 Bit set enables veto discriminator
    HLD_discriminator 0x0020 Bit set enables high-level (CNO) discriminator
    high_TCI 0x0040 Bit set enable high-range charge injection

  • Methods: BCAST
  • Ancillary files: ACD_Mask
  • Constants: None

ACD_Timing: ACD timing settings

All of the ACD timing related registers are located on the ACD readout controller (ARC) asics. The setting the widths is just a matter of optimizing efficiency against noise. Setting the delays requires doing scans to optimize for the front-end electronics shaper circuits.

  • Registers:
    Group Register Name Instances Multiplicity Subsections Type Width (bits)
    ARC hitmap_deadtime 12 1 1 int 3
    ARC hold_delay 12 1 1 int 7
    ARC hitmap_width 12 1 1 int 4
    ARC hitmap_delay 12 1 1 int xx
    ARC veto_delay 12 1 1 int 5
    ARC adc_tacq 12 1 1 int 6
    ARC veto_width 12 1 1 int xx
  • Methods: BCAST
  • Ancillary files: None
  • Constants: None

ACD_Bias: ACD Bias Dac register settings

The ACD_Bias precinct calls out the settings for the AFE bias_dac registers. These registers control the biasing of the pre-amp in the front end electronics. Changing these register will cause the pedestal values to change and would require re-configuring the ACD_Pha, ACD_Veto and ACD_Hld precincts. In normal operations we expect never to change these values.

  • Registers:
    Group Register Name Instances Multiplicity Subsections Type Width (bits)
    AFE bias_dac 12 x 18 1 1 int 6
  • Methods: BCAST or SETTINGS
    SETTINGS uses an ancillary file to set all the registers
  • Ancillary files: ACD_BiasSettings

ACD_Pha: ACD Zero-Suppression register settings

The ACD_Pha precinct controls the digital zero suppression thresholds for the PHA (long shaper) data. Any PHA value above the threshold will be read out and built into the event. Of course for non-zero suppressed mode all of the data will be read out.

  • Registers:
    Group Register Name Instances Multiplicity Subsections Type Width (bits)
    ARC pha_threshold 12 18 1 int 12

    The pha_threshold registers are called pha_threshold_0 to pha_threshold_17.

  • Methods: BCAST or CALIB
    CALIB uses an the pedestal calibration and adds an offset (default is 15 counts above pedestal).
  • Ancillary files:
    ACD_PedestalCalibration: this file contains the pedestal value for each channel.
  • Constants:
    countsAbovePedestal: offset above pedestal to set the zero-suppression threshold, nominally 15.

ACD_Veto: ACD Veto threshold register settings

  • Registers:
    Group Register Name Instances Multiplicity Subsections Type Width (bits)
    AFE veto 12 x 18 2 1 int 6

    The veto register is actually two registers ``veto_dac'' and ``veto_vernier''. However they control the same voltage level, veto_dac being a coarse knob and veto_vernier being a fine one. By design 1 veto_dac count is 32 veto_vernier counts. This is needed to for precision tunning of the ACD veto threshold and the 0.01 MIP level. Since there are two registers, the vote file xml syntax differs a bit in order to be able to specify both register values. Here is an example: 

      <AFE_veto>
            <broadcastDouble>0:0</broadcastDouble>
            <exceptDouble arc='4' afe='7'>1:4</except>
      </AFE_veto>
  • Methods: BCAST or CALIB_MIP or SETTINGS
    CALIB_MIP uses calibrations to set the thresholds in terms of MIP equivalents.
    SETTINGS uses an input file with the register settings .
  • Ancillary files:
    ACD_PedestalCalibration give pedestal values in PHA counts.
    ACD_MIPCalibration expresses MIPs in terms of PHA counts.
    ACD_VetoElectronicsCalibration maps registers settings to actual trigger points in PHA.
    ACD_VetoInMipConfiguration gives the desired threshold in MIPs for each channel.
    ACD_VetoInPhaConfiguration gives the desired threshold in PHA for each channel.
    ACD_VetoSettings gives the registers settings.
  • Constants:
    TileMip: number of MIPS to set threshold at for tiles.
    RibbonMip: number of MIPS to set threshold at for ribbons.
    NaMip: number of MIPS to set threshold at for NA (Not attached) channels.

ACD_Hld: ACD high-level discriminator (CNO) register settings

  • Registers:
    Group Register Name Instances Multiplicity Subsections Type Width (bits)
    AFE hld_dac 12 x 18 1 1 int 6
  • Methods: BCAST or SETTINGS
    SETTINGS uses an ancillary file to set all the registers.
  • Ancillary files:
    ACD_HldSettings
 

CAL: Calorimeter settings

We have split the CAL configuration into six precincts. The first two handle setting the mode (CAL_Mode) and timing (CAL_Timing) for the CAL and will be done with broadcast settings. The other four precincts (CAL_ULD, CAL_LAC, CAL_FLE, CAL_FHE) handle various settings and thresholds which require input calibrations and will vary on a channel-by-channel basis.

CAL_Mode: CAL channel masking and mode configuration

The CAL_Mode precinct controls masking various aspect of the CAL functionality and configuring the CAL Front-end electronics.

  • Registers:
    Group Register Name Instances Multiplicity Subsections Type Width (bits)
    CCC ccc_configuration 16 x 4 1 1 fields 32
    CCC layer_mask_0 16 x 4 1 1 mask 32
    CCC layer_mask_1 16 x 4 1 1 mask 32
    CRC crc_dac 16 x 4 x 4 1 1 fields 16
    CRC config 16 x 4 x 4 1 1 fields 16
    CFE config_0 16 x 4 x 4 x 12 1 1 fields 16
    CFE config_1 16 x 4 x 4 x 12 1 1 fields 16
    CFE ref_dac 16 x 4 x 4 x 12 1 1 int 16

    The breakout of the fields in the various config registers is:

    Field Mask Comments
    ccc_configuration
    data_fifo 0x0000007f When to assert almost_full on data fifo
    error_fifo 0x00003f00 When to assert almost_full on error fifo
    sum_diag_fifo 0x003f0000 When to assert almost_full on diagnostic fifo
    listen_msb 0x78000000 Number of cable not to read out
    output_enable 0x80000000 Bit set means output enabled
    crc_dac
    injection 0x0fff No Doc
    load_enable 0x4000 No Doc
    config
    always 0xa50 No Doc
    config_0
    le_gain_select 0x0007  
    he_gain_select 0x0078  
    le_range_enable 0x0080 Bit set enables readout in low range
    he_range_enable 0x0100 Bit set enables readout in high range
    use_first_range 0x0200 Bit set rorces readout in specific range
    first_range 0x0C00 Select readout range
    overwrite 0x1000 No Doc
    config_1
    preamp_auto_reset 0x0001  
    le_trigger_enable 0x0002 Bit set enables LE Trigger
    he_trigger_enable 0x0004 Bit set enables HE Trigger
    calibration_gain 0x0008 Bit set means use calibration gain
    calibration_le 0x0010 Bit set means use calibration gain for LE range
    calibration_he 0x0020 Bit set means use calibration gain for HE range
    ref_dac

  • Methods: BCAST
  • Ancillary files: CAL_Mask
  • Constants: None

CAL_Timing: CAL timing settings

The CAL timing related registers are located on the Cable Controller (CCC) and Readout Controller (CRC) electroncis. Setting the delays requires doing scans to optimize for the front-end electronics shaper circuits.

  • Registers:
    Group Register Name Instances Multiplicity Subsections Type Width (bits)
    CCC ccc_trg_alignment 16 x 4 1 1 fields 16
    CRC delay_1 16 x 4 x 4 1 1 int 16
    CRC delay_2 16 x 4 x 4 1 1 int 16
    CRC delay_3 16 x 4 x 4 1 1 int 16
  • Methods: BCAST
  • Ancillary files: None
  • Constants: None

CAL_ULD: CAL range selection discriminator settings

The CAL_ULD precinct controls the range switching discriminator CAL data.

  • Registers:
    Group Register Name Instances Multiplicity Subsections Type Width (bits)
    CFE rng_uld_dac 16 x 4 x 4 x 12 1 1 mask 16
  • Methods: BCAST | CALIB | SETTINGS
    SETTINGS uses an ancillary file to set all the registers.
    CALIB uses an ancillary calibrations file and constants to set all the registers.
  • Ancillary files: CAL_ULDSettings
  • Constants: None

CAL_LAC: CAL Zero-Suppression register settings

The CAL_LAC precinct controls zero suppression (log accept) thresholds for reading out CAL data.

  • Registers:
    Group Register Name Instances Multiplicity Subsections Type Width (bits)
    CFE log_acpt 16 x 4 x 4 x 12 1 1 mask 16
  • Methods: BCAST | CALIB | SETTINGS
    SETTINGS uses an ancillary file to set all the registers.
    CALIB uses an ancillary calibrations file and constants to set all the registers.
  • Ancillary files: CAL_LACSettings.
  • Constants: LAC_MeV: log accept threshold energy in MeV.

CAL_FLE: CAL Low-Energy threshold register settings

The CAL_FLE precinct controls low-energy (nominally 100 MeV) thresholds for generating CAL trigger requests.

  • Registers:
    Group Register Name Instances Multiplicity Subsections Type Width (bits)
    CFE fle_dac 16 x 4 x 4 x 12 1 1 mask 16
  • Methods: BCAST | CALIB | SETTINGS
    SETTINGS uses an ancillary file to set all the registers.
    CALIB uses an ancillary calibrations file and constants to set all the registers.
  • Ancillary files: CAL_FLESettings
  • Constants: FLE_MeV: Low-Energy trigger threshold energy in MeV.

CAL_FHE: CAL High-Energy threshold register settings

The CAL_FHE precinct controls high-energy (nominally 1 GeV) thresholds for generating CAL trigger requests.

  • Registers:
    Group Register Name Instances Multiplicity Subsections Type Width (bits)
    CFE fhe_dac 16 x 4 x 4 x 12 1 1 mask 16
  • Methods: BCAST | CALIB | SETTINGS
    SETTINGS uses an ancillary file to set all the registers. CALIB uses an ancillary calibrations file and constants to set all the registers.
  • Ancillary files: CAL_FHESettings
  • Constants: FHE_MeV: Low-Energy trigger threshold energy in MeV.
 

 

 

TKR: Tracker settings

We have split the TKR configuration into four precincts. The first two handle setting the mode (TKR_Mode) and timing (TKR_Timing) for the TKR and will be done with broadcast settings. A third precinct (TKR_Strips) controls masking off individual bad strips so they don't generate noise triggers. The fourth precinct (TKR_Thresh) controls the TKR threshold settings.

TKR_Mode: TKR channel masking and mode configuration

The TKR_Mode precinct controls masking various aspect of the TKR functionality and configuring the ACD Front-end electronics. Also, the TKR_Mode precinct controls the readout path of the TKR data.

  • Registers:
    Group Register Name Instances Multiplicity Subsections Type Width (bits)
    SPT low 16 x 36 1 1 int 6
    SPT high 16 x 36 1 1 int 6
    TFE calib_mask 16 x 36 x 24 1 1 mask 64
    TDC tfe_dac.injection 16 x 36 x 24 1 1 int 7
    TCC tcc_configuration 16 x 9 1 1 fields 32
    TCC input_mask 16 x 9 1 1 mask 17
    TRC trc_csr 16 x 9 x 8 1 1 fields 33
    The breakout of the fields in the various config registers is:
    Field Mask Comments
    tcc_configuration
    data_full 0x0000007f When to assert almost_full on data fifo
    error_full 0x00007f00 When to assert almost_full on error fifo
    summary_full 0x003f0000 When to assert almost_full on diagnostic fifo
    cable_length 0x78000000 Number of cable not to read out
    output_enable 0x80000000 Bit set means output enabled
    trc_csr
    size 0x0000007f  
    or_stretch 0x0001f000  
    force_no_err 0x00100000  
    tot_en 0x00200000  
    ld_size 0x20000000  
    ld_stretch 0x80000000  
    ld_st 0x200000000  

  • Methods: BCAST
  • Ancillary files: TKR_Mask: File with masked off channels.
  • Constants: None

TKR_Timing: TKR timing settings

The only TKR timing related register is on the TKR Cable Controller (TCC).

  • Registers:
    Group Register Name Instances Multiplicity Subsections Type Width (bits)
    TCC tcc_trg_align 16 x 9 1 1 int 64
  • Methods: BCAST
  • Ancillary files: None
  • Constants: None

TKR_Strips: TKR strips masking

The TKR_Strips precinct controls masking off individual bad strips. This is done my reading in an ancillary file with a list of bad strips and calculating the data masks. During orbit operations we expect to have to update the hot strips file occasionally.

  • Registers:
    Group Register Name Instances Multiplicity Subsections Type Width (bits)
    TFE trig_enable 16 x 36 x 24 1 1 mask 64
    TFE data_mask 16 x 36 x 24 1 1 mask 64
  • Methods: BCAST | SETTINGS
    SETTINGS uses an ancillary file to set all the registers.
  • Ancillary files: TKR_HotStripsCalibration
  • Constants: None

TKR_Thresh: TKR threshold register settings

  • Registers:
    Group Register Name Instances Multiplicity Subsections Type Width (bits)
    TDC tfe_dac.threshold 16 x 36 x 24 1 1 int 7

    Note: tfe_dac.threshold is actually the "threshold'' field in the tfe_dac register.
  • Methods:
    BCAST uses a single setting of all registers.
    SETTINGS uses an ancillary file to set all the registers.
  • Ancillary files: TKR_ThresholdSettings.
  • Constants: None
Owned by: Eric Charles  
Last updated by Chuck Patterson 01/22/2008