LATC Register Details

Note:

  • Group is the hardware component on which the register is located.
  • Instances is the number of specific instances of that register, broken
    down by the hardware hierarchy.
  • Multiplicity means the number of associated registers with similar names
    and functionality on each hardware instance.
  • Subsections are the number of independent data on the register.
  • If "Type" is "int'', the register should just be read as a number.
  • If "type'' is 'fields'', the register should be broken into component fields.
  • If "type'' is "mask'', the register is a bit mask where each bit enables or
    disables a channel or group of channels.

ACD Registers

Table 1:

Group Register Name Multiplicity Subsections Type Width (bits) Precinct
AEM: ACD Electronics Module. 1 Instance.
AEM aem_configuration 1 1 mask 12 GNL_Mode
AEM trgseq 1 2 fields 12 GNL_Mode
ARC: ACD Readout Controller. 12 Instances.
ARC veto_en 2 1 mask 6 ACD_Mode
ARC pha_en 2 1 mask 6 ACD_Mode
ARC max_pha 1 1 int 6 ACD_Mode
ARC pha_threshold 18 1 int 6 ACD_PHA
ARC hitmap_deadtime 1 1 int 6 ACD_Timing
ARC hold_delay 1 1 int 6 ACD_Timing
ARC hitmap_width 1 1 int 6 ACD_Timing
ARC hitmap_delay 1 1 int 6 ACD_Timing
ARC veto_delay 1 1 int 6 ACD_Timing
ARC adc_tacq 1 1 int 6 ACD_Timing
ARC veto_width 1 1 int 6 ACD_Timing
AFE: ACD Front End chips. 12 x 18 Instances.
AFE config_reg 1 1 fields 6 ACD_Mode
AFE tci_dac 1 1 int 6 ACD_Mode
AFE bias_dac 1 1 int 6 ACD_Bias
AFE veto_dac 1 1 int 6 ACD_Veto
AFE veto_vernier 1 1 int 6 ACD_Veto
AFE hld_dac 1 1 int 6 ACD_Hld

TEM Registers

Table 2:
Group Register Name Multiplicity Subsections Type Width (bits) Precinct
TEM: Tower Electronics Module. 16 Instances.
TEM data_masks 1 1 mask 16 GNL_Mode
TEM cal_trgseq 1 1 mask 16 GNL_Timing
TEM tkr_trgseq 1 1 mask 16 GNL_Timing
TIC: Trigger Interface Controller. 16 Instances.
TIC tkr_out_mask 1 1 mask 64 GNL_Mode
TIC tkr_layer_enable 1 1 mask 64 GNL_Mode
TIC cal_in_mask 1 1 mask 64 GNL_Mode

 

 


 

 

 

 

 

CAL and TKR Registers

Table 3:
CCC: CAL Cable Controller. 16 x 4 Instances.
CCC ccc_configuration 1 1 mask 16 CAL_Mode
CCC ccc_trg_alignment 1 1 mask 16 CAL_Timing
CCC layer_mask_0 1 1 mask 16 CAL_Mode
CCC layer_mask_1 1 1 mask 16 CAL_Mode
CRC: CAL Readout Controller. 16 x 4 x 4 Instances.
CRC delay_1 1 1 mask 16 CAL_Timing
CRC delay_2 1 1 mask 16 CAL_Timing
CRC delay_3 1 1 mask 16 CAL_Timing
CRC crc_dac 1 1 mask 16 CAL_Mode
CRC config 1 1 mask 16 CAL_Mode

CFE: CAL Front End chips. 16 x 4 x 4 x 12 Instances.

CFE config_0 1 1 mask 16 CAL_Mode
CFE config_1 1 1 mask 16 CAL_Mode
CFE ref_dac 1 1 mask 16 CAL_Mode
CFE rng_uld_dac 1 1 mask 16 CAL_ULD
CFE log_acpt 1 1 mask 16 CAL_LAC
CFE fle_dac 1 1 mask 16 CAL_FLE
CFE fhe_dac 1 1 mask 16 CAL_FHE
SPT: TKR Splits. 16 x 36 Instances.
SPT low 1 1 int 6 TKR_Mode
SPT high 1 1 int 6 TKR_Mode
TFE: TKR Front End chips. 16 x 36 x 24 Instances.
TFE calib_mask 1 1 mask 64 TKR_Mode
TFE trig_enable 1 1 mask 64 TKR_Strips
TFE data_mask 1 1 mask 64 TKR_Strips
TDC: TKR Front End dac settings. 16 x 36 x 24 Instances.
TDC tfe_dac.threshold 1 1 int 64 TKR_Thresh
TDC tfe_dac.injection 1 1 int 64 TKR_Mode
TCC: TKR Cable Controller. 16 x 8 Instances.
TCC tcc_trg_align 1 1 int 64 TKR_Timing
TCC tcc_configuration 1 1 fields 64 TKR_Mode
TCC input_mask 1 1 mask 64 TKR_Mode
TRC: TKR Readout Controller. 16 x 8 x 9 Instances.
TRC trc_csr 1 1 fields 64 TKR_Mode

GEM Registers

Table 4:
Group Register Name Multiplicity Subsections Type Width (bits) Precinct
GEM r 54 2 mask 32 TRG_ROI
GEM conditions 32 8 int 32 TRG_GEM
GEM configuration 1 1 fields 1 TRG_GEM
GEM engine 16 1 fields 32 TRG_GEM
GEM periodic_rate 1 1 fields 32 TRG_GEM
GEM periodic_mode 1 1 fields 2 TRG_GEM
GEM periodic_limit 1 1 fields 32 TRG_GEM
GEM window_open_mask 1 1 fields 8 TRG_GEM
GEM window_width 1 1 int 5 TRG_GEM
GEM towers 4 4 mask 12 TRG_GEM
GEM tiles 24 2 mask 18 TRG_GEM
GEM acd_cno 1 1 mask 12 TRG_GEM
GEM tower_busy 1 1 mask 16 TRG_GEM
GEM external 1 1 mask 1 TRG_GEM

 


Owned by: Eric Charles
Last updated by: Chuck Patterson 01/22/2008